The present invention relates to a polishing method and apparatus. More particularly, the present invention relates to a polishing method and apparatus wherein a Cu layer formed on a substrate is polished by a chemical and mechanical polishing (CMP) process, in the case that Cu (copper) wiring is to be formed on the substrate, e.g. a semiconductor wafer.
Conventionally, to form circuit wiring patterns or interconnections in a semiconductor substrate, a conductor film is deposited on the substrate surface by using sputtering or other similar process, and then unnecessary portions of the film are removed by chemical dry etching using a pattern mask, e.g. a resist pattern mask.
As a material for forming circuit wiring patterns, aluminum (Al) or an aluminum alloy is generally used. However, as the degree of integration of semiconductor devices increases, wiring patterns are becoming smaller and finer, resulting in an increase in current density, with a consequent increase in thermal stress and temperature. Such a phenomenon becomes more pronounced as Al or other films for wiring patterns are made thinner due to resulting problems of stress migration and electromigration, and there is a possibility that wiring patterns may become disconnected or short-circuit.
Accordingly, it is necessary for a material having higher electric conductivity, such as copper, to be employed in forming wiring patterns, to thereby avoid excessive heat generation during energization thereof. However, copper and copper alloys are difficult to etch using conventional dry etching processes. Therefore, it is difficult to adopt the above-described method, in which patterns are formed after a film has been deposited on the entire substrate surface. In view of this problem, there has been considered adoption of a process by which the substrate surface is preformed with grooves in a predetermined pattern for wiring, and then copper or a copper alloy is filled into the grooves. This method makes redundant the process for removing unnecessary portions of the film by etching, and it is necessary only to carry out a polishing process for removing steps on the surface after the grooves have been filled with copper or a copper alloy. Further, the latter mentioned process is advantageous in that it is possible to form simultaneously wiring holes for interconnection between upper and lower layers of a multilayer circuit.
However, the aspect ratio (i.e. the ratio of the depth to the diameter or the width) of such wiring grooves or wiring holes has become high as the line width of wiring patterns has become increasingly fine. As a result, it is difficult to fill uniformly such wiring grooves or wiring holes with a metal by using a sputtering process. Meanwhile, a process which is used generally as a method for deposition of various materials exists which is known as chemical vapor deposition (CVD). In the case of copper or a copper alloy, however, it is difficult to prepare an appropriate gas material for the CVD process. In addition, when an organic material is employed, carbon (C) may become mixed in with the deposited film, causing an undesirable increase in migration problems.
Under these circumstances, a method has been proposed in which a substrate is dipped in a plating solution and subjected to electroless plating or electroplating of copper (Cu), and thereafter, unnecessary portions of the Cu deposited on the substrate surface are removed by a chemical and mechanical polishing (CMP) process. Such film deposition by plating allows wiring grooves of high aspect ratio to-be filled uniformly with Cu of high electrical conductivity. In the CMP process, a semiconductor wafer held by a top ring is pressed against a polishing cloth bonded to the surface of a turntable, and while the wafer is thus held, a polishing solution containing abrasive grains is supplied to the polishing cloth, whereby the Cu layer on the semiconductor wafer is polished both chemically and mechanically.
In polishing a Cu layer by the CMP process it is necessary to selectively remove the Cu layer from the semiconductor substrate while leaving only those portions of the Cu layers filled in the grooves forming Cu wiring. More specifically, portions of the Cu layer deposited in regions other than the grooves forming Cu wiring are required to be removed before the underlying oxide film (SiO2) is exposed. In such a case, if the Cu layer is over-polished to an extent that the portions of the Cu layer in the grooves forming Cu wiring are polished along with the oxide film (SiO2), an undesirable rise in circuit resistance will occur. If this happens, the entire semiconductor substrate becomes waste. Conversely, if the Cu layer is left on the oxide film due to insufficient polishing, adequate circuit separation cannot be accomplished, which may lead to short circuiting. Thus, re-polishing must be performed thereby increasing manufacturing costs.
FIGS. 9(a) to 9(c) are schematic views showing a process sequence for forming Cu wiring by the conventional CMP process. As shown in FIG. 9(a), wiring grooves 30 formed in the surface of a semiconductor substrate are filled with a Cu layer 31, and the entire substrate surface is then covered with the Cu layer 31. At this time, the surface of the Cu layer 31 is formed with steps (recesses and projections). In this state, the CMP process is started. As shown in FIG. 9(b), the Cu layer 31 is polished under first polishing conditions in a first polishing step until a barrier metal layer (made of Ta or TaN, for example) 32 is exposed.
Next, as shown in FIG. 9(c), the barrier metal layer 32 is polished under second polishing conditions in a second polishing step to remove the barrier metal until an oxide film (SiO2) 33 is exposed in regions other than portions where the Cu layers 31 are formed in the wiring grooves 30. In such a polishing process, the common practice is to use a slurry (polishing solution) exhibiting a high selectivity ratio of the polish rate (polishing speed) for Cu to that for the barrier metal in the first polishing step. That is, a slurry capable of readily grinding Cu but incapable of readily grinding the barrier metal is used in the first polishing step. The second polishing step uses a slurry (polishing solution) exhibiting a tendency opposite to that of the slurry used in the first polishing step, i.e. a slurry exhibiting a high polish rate (polishing speed) for the barrier metal and a low polish rate for Cu.
The above-described CMP process suffers, however, from some problems. Namely, when a device is polished using the CMP process, if the second polishing step is started when a slight amount of Cu remains on the barrier metal in the first polishing step, Cu cannot be easily or sufficiently removed in the second polishing step. This results in regions other than where a slight amount of Cu remains over-polished. Consequently, an undesirable rise in circuit resistance in the over-polished regions occurs. Such over-polishing occurs as dishing in which Cu wiring portions in grooves are over-polished in a dish-like shape, or oxide erosion in which Cu wiring patterns located proximate to each other separate off, along with the oxide film.
An object of the present invention is to solve the above-described problems associated with the CMP process and to provide a polishing method and apparatus capable of removing uniformly a Cu layer formed on a substrate, e.g. a semiconductor wafer, and of planarly and uniformly polishing Cu wiring portions formed in fine grooves and/or fine holes formed in the substrate surface without causing over-polishing such as dishing or erosion.
To attain the above-described object, the present invention provides a polishing method for polishing a Cu layer formed on a semiconductor substrate by a chemical and mechanical polishing process to form Cu wiring on the semiconductor substrate. The polishing method includes a first polishing step of preparing a semiconductor substrate having a Cu layer formed so as to fill wiring grooves formed in a surface of the semiconductor substrate and to cover regions of the substrate surface where no wiring groove is formed, and polishing the semiconductor substrate until the Cu layer is polished to a predetermined thickness by bringing the semiconductor substrate into sliding contact with a polishing surface on a turntable. The polishing method further includes a second polishing step of polishing the semiconductor substrate after the first polishing step until the Cu layer formed on the surface of the semiconductor substrate is removed, except for portions of the Cu layer formed to fill the wiring grooves, and a barrier metal layer is also removed by bringing the semiconductor substrate into sliding contact with the polishing surface on the turntable.
In addition, the present invention provides a polishing apparatus for polishing a Cu layer on a semiconductor substrate to form Cu wiring on the semiconductor substrate. The polishing apparatus includes a first turntable having a polishing surface for polishing a semiconductor substrate having a Cu layer formed so as to fill wiring grooves formed in a surface of the semiconductor substrate and to cover regions of the substrate surface where no wiring groove is formed, by bringing the semiconductor substrate into sliding contact with the polishing surface until the Cu layer is polished to a predetermined thickness. A second turntable has a polishing surface for polishing the semiconductor substrate polished with the polishing surface of the first turntable by bringing the semiconductor substrate into sliding contact with the polishing surface of the second turntable until the Cu layer on the surface of the semiconductor substrate is removed, except for portions of the Cu layer formed to fill the wiring grooves, and a barrier metal layer is also removed. The polishing apparatus further includes a sensor for detecting an end point of polishing carried out on the polishing surface of the first turntable and an another sensor for detecting an end point of polishing carried out on the polishing surface of the second turntable.
According to the present invention, at the first polishing step, polishing is carried out until the thickness of the Cu layer formed on the semiconductor substrate reaches a predetermined value. In the first polishing step, only the Cu layer is polished, and the barrier metal layer is not polished. Therefore, during polishing in the first polishing step, the thickness of the Cu layer is continuously measured with a first sensor. When the value detected with the sensor reaches a predetermined threshold value, the first polishing step is terminated.
Next, in the second polishing step, the Cu layer and the barrier metal layer are removed until the underlying oxide film is exposed in regions other than portions where the Cu layer is formed in the wiring grooves. In the second polishing step, both the Cu layer and the barrier metal layer are polished. Therefore, a slurry (polishing solution) exhibiting a low selectivity ratio of polish rate (polishing speed) for Cu to that for the barrier metal is used. During polishing in the second polishing step, the thickness of the Cu layer and the thickness of the barrier metal layer are continuously measured by another sensor. The CMP process is terminated when it is detected by the another sensor that the barrier metal layer has been removed completely. In the second polishing step, a slurry (polishing solution) that also provides a predetermined polish rate (polishing speed) for the oxide film is used so as to remove the barrier metal layer completely.